
DS3911
Temperature-Controlled, Nonvolatile,
I2C Quad DAC
16
Maxim Integrated
Register Description
This register map shows each byte/word (2-byte) in terms of its row and byte/word placement in the memory. The first
byte in the row is located in memory at the row address (hexadecimal) in the leftmost column. Each subsequent byte/
word on the row is one/two memory locations beyond the previous byte/word’s address. A total of 8 bytes are present
Lower Memory Register Map
Lower Memory Register Descriptions
Lower Memory, Register 00h: CTRL
LOWER MEMORY
ADDR
(HEX)
WORD 0
WORD 1
WORD 2
WORD 3
BYTE 0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
BYTE 5
BYTE 6
BYTE 7
00h
CTRL
MODE
SRAM
TINDEX
TEMP VALUE
VCC VALUE
08h
—
10h
DAC3 VALUE
DAC2 VALUE
DAC1 VALUE
DAC0 VALUE
78h
DAC3 POR
DAC2 POR
DAC1 POR
DAC0 POR
POWER-ON VALUE
00h
ACCESS
R/W
MEMORY TYPE
Volatile
00h
DONETEMP
DONEVCC
SRAM
TS3
TS2
TS1
TS0
BIT 7
BIT 0
BIT 7
DONETEMP: Done Temp Status
0 = Temperature conversion in progress.
1 = Temperature conversion completed since this bit was last cleared.
BIT 6
DONEVCC: Done VCC Status
0 = VCC conversion in progress.
1 = VCC conversion completed since this bit was last cleared.
BITS 5:4
SRAM: General-Purpose SRAM. These bits have no affect on device operation.
BITS 3:0
TS[3:0]: Table Select. The device’s memory tables are accessed by writing the desired table
value in this bit field. The device only contains four addressable memory tables, 04h–07h, and
therefore the values listed below are the only usable options.
TS[3:0]
TABLE SELECTED
CORRESPONDING DAC LUT
0100b
04h
0
0101b
05h
1
0110b
06h
2
0111b
07h
3